The present invention relates to a semiconductor device having an anti-reflective film on an interconnect line and a method for manufacturing the same and, in particular, to a dry etching method for forming such an interconnect configuration as to allow an insulating interlayer to be deposited between interconnect lines in a general MOS product, such as a MOS memory product and MOS logic product and a semiconductor device manufactured using such method.
In a semiconductor integrated circuit such as a MOS memory product and MOS logic product, a high integration density has recently been further advanced and the design size of the interconnect line is of the order of below 1 .mu.m. With this advance, it has been becoming difficult to directly pattern the resist film coated on an interconnect material, such as aluminum, by a photolithography technique. That is, when the circuit pattern is transferred by an exposure apparatus to the resist film, the side wall of the patterned resist film is exposed with light reflected by an interconnect material of an underlying film. For this reason, the shaping of the pattern varies, thus leading to a fall in the accuracy of the pattern.
Normally, an anti-reflective film of a lower reflectivity material is deposited on the interconnect material and the resist film is coated on the anti-reflective film and patterned by photolithography technique. In this case, it is possible to prevent light from being reflected on the underlying film upon patterning.
If, on the other hand, the RIE (reactive ion etching) characteristic of the anti-reflective film is prominently different from that of the interconnect material providing the underlying film, then it is not possible to etch the anti-reflective film and interconnect material at one RIE step and it is necessary to effect the etching of the anti-reflective film and that of the interconnect material in separate steps and separate chambers. It is considered convenient to be able to use an anti-reflective film spin-coatable as the resist film. For the case of the interconnect material being an aluminum film, however, the RIE characteristic of the spin-coatable anti-reflective film becomes different from that of the aluminum film. This necessitates etching the anti-reflective film and interconnect material in separate steps and hence increasing the number of steps of forming the interconnect line. From this viewpoint, use is normally made, as an anti-reflective film for the aluminum film, of the material TiN etchable together with the aluminum film.
FIGS. 4A to 4C are cross-sectional views showing a conventional interconnect line forming process.
First, a well, not shown, is formed in a semiconductor substrate 11, an element isolation area, not shown, is formed by an LOCOS method for instance, and a gate oxide film, gate electrode and source/drain structure are formed to provide a transistor.
Then an insulating film 5 is deposited on the whole surface of a semiconductor substrate 11 and contact holes, not shown, are opened, a Ti film of, for example, 20 nm thick is deposited on the whole surface and a TiN film of, for example, 70 nm thick is formed on the Ti film. A barrier metal 4 is formed with the Ti film and TiN film. An Ag alloy film 3 of, for example, 600 nm thick is deposited on the barrier metal film 4 and a TiN film 2 of, for example, 30 nm thick is deposited on the Al alloy film 3. The TiN film 2 serves as an anti-reflective film.
A resist film 1 of, for example, 1500 nm thick is coated on the anti-reflective film 2 and patterned by the photolithography technique. FIG. 4A shows a cross-sectional view showing a semiconductor device structure at that stage of manufacture.
Then the anti-reflective film 2, Al alloy film 2 and barrier metal film 4 are etched, by the RIE technique, with the resist film 1 used as a mask. FIG. 4B is a cross-sectional view showing the semiconductor device at this stage of manufacture. Upon the etching of the Al alloy film 3, a decomposition product of the resist film 1 is created, by slightly etching the resist film 1 by virtue of the RIE method, so that the product is deposited on the side wall of the Ag alloy film 2 being etched to provide a side wall protection film 6. For this reason, the Al alloy film 3 is etched anisotropically. At the initial stage of etching the Al alloy film, however, the decomposition product of the resist film 1 is not adequately supplied to the side wall of the Al alloy film. For this reason, the Al alloy film 3 immediately below the anti-reflective film 2 is etched, to some extent, in a direction parallel to the substrate 11. As a result, the anti-reflective film 2 has a broader width than that of the immediately underlying Al alloy film 3 and extends, for example, about 50 nm, sideway relative to the Al alloy film 3, a state which will be referred to, hereinafter, as an "overhanging" state.
Then the resist film 1 is removed and a silicon oxide film of, for example, 1300 nm thick is deposited, by a plasma-CVD (chemical vapor deposition) method, as an insulating interlayer 7, on the resultant semiconductor structure. FIG. 4C is a cross-sectional view showing a semiconductor device at this stage of manufacture. Upon the removal of the resist film, the decomposition product, that is, the side wall protection film 6, of the resist film is removed to expose the overhanging type anti-reflective film 2. The insulating interlayer 7 formed by the CVD method faithfully reflects the shape of the interconnect line to be buried. For this reason, the insulating interlayer 7 is grown, while reflecting the overhanging shape, so that a void 8 is created in the insulating interlayer 7 between adjacent interconnect lines. Such void 8, upon the planarization of the insulating interlayer 7, is exposed on the surface of the insulating interlayer 7. In this case, such void is groove-like and, if a second interconnect line is formed as it is, there is a possibility that there will occur a breakage in the second interconnect layer or a short-circuiting of the interconnect line due to the interconnect material entering in the groove.
If necessary, a multi-level interconnect structure is formed and a passivation film is deposited.
In this way, the anti-reflective film, being so overhung, creates voids, thus presenting a problem.